1. Technical Field
This invention relates in general to gate circuits, and more particularly, to a gate circuit formed of a combination of metal-oxide-semiconductor field-effect transistors and bipolar transistors (herein BiCMOS gate circuit) for fast switching of large loads.
2. Description of the Prior Art
Numerous BiCMOS gate circuits are available in the open literature. These circuits generally seek to achieve high speed operation with low power consumption. By way of example, reference is made to the circuits disclosed in U.S. Pat. No. 4,829,201, entitled "Gate Circuit of Combined Field-Effect and Bipolar Transistors," and IEEE International Solid-State Circuits Conference article entitled "High-Speed Digital BiCMOS ICs." Any enhancements to the speed of operation and/or power consumption characteristics of such circuits are considered significant in BiCMOS gate circuit technology.
As a state-of-the-art type example, a typical BiCMOS NAND pull-up/pull-down gate circuit 11 is depicted in FIG. 1. As depicted, BiCMOS NAND circuit 11 includes a pull-down circuit 10 and a pull-up circuit 12. Once activated, pull-up circuit 12 functions to provide a sharp pull-up transition on a load, while conversely pull-down circuit 10 functions to provide a sharp pull-down transition on the load once the pull-up circuit becomes inactive. Numerous alternate circuit embodiments for both pull-down circuit 10 and pull-up circuit 12 are available in the open literature. Since the present invention relates to the pull-down function, a detailed description of only the pull-down portion of this conventional BiCMOS gate circuit configuration is provided.
Circuit 10 includes a bipolar transistor Q.sub.1 having a collector "C" connected to the output of BiCMOS NAND circuit 11, and n series connected n-channel metal-oxide-semiconductor field-effect transistors (hereinafter NFETs) T.sub.o . . . T.sub.n connected between the collector "C" and base "B" of transistor Q.sub.1. Circuit inputs A.sub.0 . . . A.sub.n are each respectively fed to the gate "G" of one of the NFETs T.sub.0 . . . T.sub.n. NFETs T.sub.0 . . . T.sub.n are serially connected such that the drain "D" of the first NFET T.sub.0 is connected to the collector "C" of transistor Q.sub.1 and the source "S" of the nth NFET T.sub.n is connected to the base "B" of transistor Q.sub.1. Transistor Q.sub.1 comprises an npn type transistor with its emitter "E" connected to ground. A bleeder resistor "R", connected between base "B" of transistor Q.sub.1 and ground, is provided for discharging charge from base "B" when transistor Q.sub.1 is switched to an off state from an on state. In the NAND gate configuration shown, when inputs A.sub.0 . . . A.sub.n are high, NFETs T.sub.0 . . . T.sub.n are all in an on state and a base current (from load capacitance) begins to flow.
Transistor Q.sub.1 amplifies this base current, and thereby quickly discharges the output capacitance through collector "C" to emitter "E" and hence ground.
Theoretically, base "B" will rise to a diode drop, i.e., 0.7 volts, thereby turning transistor Q.sub.1 on strongly. NFETs T.sub.0 . . . T.sub.n will conduct until collector "C" falls to 0.7 volts. At that time, the drain to source voltage V.sub.DS across NFETs T.sub.0 . . . T.sub.n will be zero and no more current will flow in the circuit. Saturation of transistor Q.sub.1 is therefore avoided by design because collector "C" voltage cannot go lower than base "B" voltage.
In practice, however, peak voltage at base "B" may actually rise to 1.4 volts instead of the "textbook" value of 0.7 volts. A number of factors can combine to produce such an increased base voltage. For example, current densities in BiCMOS gate devices are very high, meaning that the actual junction turn on voltage is in practice slightly greater than 0.7 volts. Further, internal parasitic resistances in series with the emitter and base combine to further limit performance of the circuit. Parasitic resistances can contribute up to 0.5 volts to transistor Q.sub.1 turn on voltage.
A high base "B" voltage detracts directly from the voltage between gate and source V.sub.GS of NFETs T.sub.0 . . . T.sub.n, thereby reducing the conductance of the NFET stack. A lower conductance reduces base "B" rise time, which produces a slower pull-down circuit. The loss of NFET stack conductance becomes more significant when the voltage V.sub.CC (not shown) applied across the BiCMOS gate circuit is reduced. The voltages input A.sub.0 . . . A.sub.n at the gates of the NFET stack are from previous logic stages, and a high voltage of a previous stage will necessarily track V.sub.CC, i.e., the power supply across the entire circuit, which in turn effects the gate to source voltage V.sub.GS across NFETs T.sub.o . . .T.sub.n. Further, performance can be effected by increasing the number of FETs in the stack. The more devices in series (e.g., for an AND or NAND gate), the worse the conductance of the field-effect transistor stack and, therefore, the performance of the pull-down circuit.
Thus, an enhanced BiCMOS gate pull-down circuit achieving higher speed operation with lower power consumption than presently available BiCMOS gate circuits is believed desirable and of significant value to the industry.